Fpga-cores code is divided in synthesizable, simulation helpers and testbenches..

This library provides some extra bits of code that are not found in the standard VHDL libraries.

The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks.

A Tiny and Platform-Independent True Random Number Generator for any FPGA.

Customizable microcontroller-like system on chip written in platform-independent VHDL.

General cores is a library of widely used cores but still small enough not to require a dedicated repository.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks.

GHDL Language Server Protocol (LSP) is a server for VHDL based on GHDL.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

This package provides a program to transfer a bitstream to an FPGA. To use openfpgaloader without root privileges it is necessary to install the necessary udev rules. This can be done by extending udev-service-type in the operating-system configuration file with this package, as in:

(udev-rules-service 'openfpgaloader openfpgaloader #:groups '("plugdev")

Additionally, the plugdev group should be registered in the supplementary-groups field of your user-account declaration. Refer to info "(guix) Base Services" for examples.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

Yosys synthesizes Verilog-2005.

Yosys synthesizes Verilog-2005.

Yosys synthesizes Verilog-2005.

This plugin provides a shared library module for Yosys to implement logical synthesis of VHDL designs.

Yosys synthesizes Verilog-2005.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

This package is a waveform viewer for FST files.

sequencing partial combinations

Implementation of the XDG Base Directory Specification

Bindings to the IUP GUI library

explicitly implicit renaming