Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Eqy is a front-end driver program for Yosys-based formal hardware equivalence checking. It performs formal verification on two designs, such as ensuring that a synthesis tool has not introduced functional changes into a design, or ensuring that a design refactor preserves correctness in all conditions.

Nextpnr is a portable FPGA place and route tool.

This package is a waveform viewer for FST files.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

Sigrok-cli is a command-line frontend for sigrok.

This package provides a library to turn Python into a hardware description and verification language.

UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.

OpenBoardView is a viewer for BoardView files, which present the details of a printed circuit board (PCB). It comes with features such as:

• Dynamic part outline rendering, including complex connectors

• Annotations, for leaving notes about parts, nets, pins or location

• Configurable colour themes

• Configurable DPI to facilitate usage on 4K monitors

• Configurable for running on slower systems

• Reads FZ (with key), BRD, BRD2, BDV and BV* formats.

The Dirtywave M8 Tracker is a portable sequencer and synthesizer, featuring 8 tracks of assignable instruments such as FM, waveform synthesis, virtual analog, sample playback, and MIDI output. It is powered by a Teensy micro-controller and inspired by the Gameboy tracker Little Sound DJ. m8c is a client for M8 Headless which allows one to install the M8 firmware on any Teensy.

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

Magic is an interactive EDA layout tool. It can run DRC and LVS tests and can assist with automatic routing.

qucsrflayout command exports RF schematics to KiCad layouts and OpenEMS scripts.

The codePyVcd Python library writes VCD files as specified in IEEE 1364-2005.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Prjpeppercorn includes programming tools for GateMate architecture from Cologne Chip. It also provides data needed to produce a nextpnr chip database Cologne Chip's GateMate architecture.

This package provides an extension to cocotb in the form of AXI, AXI lite, and AXI stream modules.

OSVVM is a verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability for FPGA or ASIC verification.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.