This package provides a VHDL compiler and simulator.

This is a pythonized, kind of reverse engineered version of original AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout are also taken from the original.

The JSON-for-VHDL library provides a parser to query JSON data structures from external files on disk. It provides a context to be used in the declarative section of design units.

sby is a front-end program for Yosys-based formal hardware verification flows.

Magic is an interactive EDA layout tool. It can run DRC and LVS tests and can assist with automatic routing.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

sby-gui is a GUI for front-end driver program for codeyosys-based formal hardware verification flows.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

The project Apycula provides tools to support development and generating bitstreams with Gowin FPGAs.

Libfst is a small library used to read and write FST format waveforms.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

The codePyVcd Python library writes VCD files as specified in IEEE 1364-2005.

Cocotb-bus provides a set of utilities, test benches and reusable bus interfaces to be used with cocotb.

PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI for sigrok.

Nextpnr is a portable FPGA place and route tool.

Libsigrokdecode is a shared library written in C, which provides (streaming) protocol decoding functionality.

This package provides a library to turn Python into a hardware description and verification language.

UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.

Eqy is a front-end driver program for Yosys-based formal hardware equivalence checking. It performs formal verification on two designs, such as ensuring that a synthesis tool has not introduced functional changes into a design, or ensuring that a design refactor preserves correctness in all conditions.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

Verilator transforms the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files.

Open Logic implements commonly used design units in a reusable and vendor/tool-independent way. It is written following the VHDL 2008 standard, but can also be used from System Verilog.

Comedilib is a user-space library that provides a developer-friendly interface to Comedi devices. Comedi is a collection of drivers for a variety of common data acquisition plug-in boards. The drivers are implemented as a core Linux kernel module providing common functionality and individual low-level driver modules.