Charlib is an EDA tool used to extract timing and power characteristics from CMOS combinational and sequential standard-cells. It is compatible with ngspice and Xyce.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

ciel downloads and installs open-source PDKs which are used for chip design and EDA.

A minimal application for the qcsxcad library which is used to describe geometrical objects and their physical and non-physical properties.

Libfst is a small library used to read and write FST format waveforms.

This package provides an extension to cocotb in the form of AXI, AXI lite, and AXI stream modules.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

The codePyUCIS library provides two APIs for creating and accessing coverage data via the UCIS data mode.

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

This package provides CERN's KiCad component libraries, including schematic symbols, footprints, a SQLite-backed database library, and KiCad library tables. The libraries are generated from CERN's Altium Designer libraries.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

PyXHDL replaces HDL code by Python, generating VHDL (>= 2008) and Verilog (SystemVerilog >= 2012) code to be used for synthesis and simulation.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

The Dirtywave M8 Tracker is a portable sequencer and synthesizer, featuring 8 tracks of assignable instruments such as FM, waveform synthesis, virtual analog, sample playback, and MIDI output. It is powered by a Teensy micro-controller and inspired by the Gameboy tracker Little Sound DJ. m8c is a client for M8 Headless which allows one to install the M8 firmware on any Teensy.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

Surelog is a pre-processor, parser, elaborator and UHDM compiler. It provides IEEE design, a C/C++ VPI and a Python AST API.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Icarus Verilog is a Verilog/SystemVerilog EDA compiler that generates code employed by back-end tools. It operates compiling source code written in Verilog (IEEE-1364) and SystemVerilog (IEEE-1800) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

This package is a waveform viewer for FST files.

Surfer is a waveform viewer used in EDA with a focus on usability and extensibility.

csxcad is a C++ library to describe geometrical objects and their physical or non-physical properties for electromagnetics simulations.

qrouter is an ASICs tool intended for digital chip design. It creates the detailed routes for layouts of digital circuits and generates metal layers and vias.

Mcy is an EDA tool to help digital designers and project managers understand and improve testbench coverage.