HAL is an EDA comprehensive netlist reverse engineering and manipulation framework. It provides a framework to parse netlists of arbitrary sources, e.g., FPGAs or ASICs, into a graph-based netlist representation, providing the necessary built-in tools for traversal and analysis of the included gates and nets.

PyUVM is a Python implementation of the UVM, as defined in the IEEE 1800.2 standard. It uses cocotb to interact with simulators and schedule simulation events. It implements the most commonly used sections of the IEEE 1800.2 standard.

Libsigrokdecode is a shared library written in C, which provides (streaming) protocol decoding functionality.

Verilator is an EDA tool intended to transform the specified Verilog or SystemVerilog HDL code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single or multi-threaded .cpp and .h files.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

lctime extracts timing and power characteristics of CMOS standard-cells. It simulates the netlists of the cells with ngspice and writes the characterization result in a liberty library file.

GUI library for csxcad --- a library for describing geometrical objects and their properties. This library is used in appcsxcad which provides a standalone graphical frontend to {csxcad

Comedilib is a user-space library that provides a developer-friendly interface to Comedi devices. Comedi is a collection of drivers for a variety of common data acquisition plug-in boards. The drivers are implemented as a core Linux kernel module providing common functionality and individual low-level driver modules.

ABC is a program for sequential logic synthesis and formal verification.

fftgen produces FFT hardware designs in Verilog.

Libserialport is a minimal shared library written in C that is intended to take care of the OS-specific details when writing software that uses serial ports.

The codePyVcd Python library writes VCD files as specified in IEEE 1364-2005.

Xschem is an X11 schematic editor written in C and focused on hierarchical and parametric design. It can generate VHDL, Verilog or Spice netlists from the drawn schematic, allowing the simulation of the circuit.

OpenBoardView is a viewer for BoardView files, which present the details of a printed circuit board (PCB). It comes with features such as:

• Dynamic part outline rendering, including complex connectors

• Annotations, for leaving notes about parts, nets, pins or location

• Configurable colour themes

• Configurable DPI to facilitate usage on 4K monitors

• Configurable for running on slower systems

• Reads FZ (with key), BRD, BRD2, BDV and BV* formats.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

The project Apycula provides tools to support development and generating bitstreams with Gowin FPGAs.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

This package provides a library to turn Python into a hardware description and verification language.

UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

GNUcap is a circuit analysis package used for EDA. It offers a general purpose circuit simulator and can perform DC and transient analyses, fourier analysis and AC analysis. The engine is designed to do true mixed-mode simulation.