Yosys synthesizes Verilog-2005.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

Cocotb-bus provides a set of utilities, test benches and reusable bus interfaces to be used with cocotb.

Comedilib is a user-space library that provides a developer-friendly interface to Comedi devices. Comedi is a collection of drivers for a variety of common data acquisition plug-in boards. The drivers are implemented as a core Linux kernel module providing common functionality and individual low-level driver modules.

Camv-rnd is a viewer for PCB supporting gerber, excellon and g-code. It is part of the RiNgDove EDA suite.

This package provides a library to turn Python into a hardware description and verification language.

fftgen produces FFT hardware designs in Verilog.

Project Trellis is a Nextpnr backend compatible with ECP5 FPGAs. The following features are currently available:

• logic slice functionality, including carries

• distributed RAM inside logic slices

• all internal interconnect

• basic IO, including tristate

• block RAM, using inference or manual instantiation

• multipliers using manual instantiation

• global networks and PLLs

• transcievers (DCUs.)

libsigrok is a shared library written in C which provides the basic hardware access drivers for logic analyzers and other supported devices, as well as input/output file format support.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

Xschem is an X11 schematic editor written in C and focused on hierarchical and parametric design. It can generate VHDL, Verilog or Spice netlists from the drawn schematic, allowing the simulation of the circuit.

This package implements a functionality to create project files for supported tools and run them in batch or GUI mode. All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files,memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.

Prjpeppercorn includes programming tools for GateMate architecture from Cologne Chip. It also provides data needed to produce a nextpnr chip database Cologne Chip's GateMate architecture.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

OpenBoardView is a viewer for BoardView files, which present the details of a printed circuit board (PCB). It comes with features such as:

• Dynamic part outline rendering, including complex connectors

• Annotations, for leaving notes about parts, nets, pins or location

• Configurable colour themes

• Configurable DPI to facilitate usage on 4K monitors

• Configurable for running on slower systems

• Reads FZ (with key), BRD, BRD2, BDV and BV* formats.

Libfst is a small library used to read and write FST format waveforms.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

The JSON-for-VHDL library provides a parser to query JSON data structures from external files on disk. It provides a context to be used in the declarative section of design units.

UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.