_            _    _        _         _
      /\ \         /\ \ /\ \     /\_\      / /\
      \_\ \       /  \ \\ \ \   / / /     / /  \
      /\__ \     / /\ \ \\ \ \_/ / /     / / /\ \__
     / /_ \ \   / / /\ \ \\ \___/ /     / / /\ \___\
    / / /\ \ \ / / /  \ \_\\ \ \_/      \ \ \ \/___/
   / / /  \/_// / /   / / / \ \ \        \ \ \
  / / /      / / /   / / /   \ \ \   _    \ \ \
 / / /      / / /___/ / /     \ \ \ /_/\__/ / /
/_/ /      / / /____\/ /       \ \_\\ \/___/ /
\_\/       \/_________/         \/_/ \_____\/
abc-yosyshq 0.53
Dependencies: readline@8.1.2
Channel: guix
Location: gnu/packages/fpga.scm (gnu packages fpga)
Home page: https://github.com/YosysHQ/abc/
Licenses: non-copyleft
Synopsis: Sequential logic synthesis and formal verification
Description:

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

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