_            _    _        _         _
      /\ \         /\ \ /\ \     /\_\      / /\
      \_\ \       /  \ \\ \ \   / / /     / /  \
      /\__ \     / /\ \ \\ \ \_/ / /     / / /\ \__
     / /_ \ \   / / /\ \ \\ \___/ /     / / /\ \___\
    / / /\ \ \ / / /  \ \_\\ \ \_/      \ \ \ \/___/
   / / /  \/_// / /   / / / \ \ \        \ \ \
  / / /      / / /   / / /   \ \ \   _    \ \ \
 / / /      / / /___/ / /     \ \ \ /_/\__/ / /
/_/ /      / / /____\/ /       \ \_\\ \/___/ /
\_\/       \/_________/         \/_/ \_____\/
verilator 4.110
Dependencies: perl@5.36.0 python@3.11.11 systemc@3.0.1
Channel: gn-bioinformatics
Location: gn/packages/fpga.scm (gn packages fpga)
Home page: https://www.veripool.org/verilator/
Licenses: LGPL 3
Synopsis: Verilog/SystemVerilog simulator
Description:

Verilator transforms the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files.

verilator 5.040
Dependencies: perl@5.36.0 python@3.11.11 systemc@3.0.1
Channel: guix
Location: gnu/packages/electronics.scm (gnu packages electronics)
Home page: https://www.veripool.org/verilator/
Licenses: LGPL 3
Synopsis: Verilog/SystemVerilog simulator
Description:

Verilator transforms the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files.

Total results: 2