libpsf is a c++ library that reads Cadence PSF binary waveform files.

Gerbv is a viewer for files in the Gerber format (RS-274X only), which is commonly used to represent printed circuit board (PCB) layouts. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place files.

ABC is a program for sequential logic synthesis and formal verification.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

This package provides an extension to cocotb in the form of AXI, AXI lite, and AXI stream modules.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

Nextpnr is a portable FPGA place and route tool.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

Sch-rnd is a standalone and workflow agnostic schematics capture tool for PCB, part of the RiNgDove EDA suite.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

OSVVM is a verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability for FPGA or ASIC verification.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

This package implements a functionality to create project files for supported tools and run them in batch or GUI mode. All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files,memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.

Libserialport is a minimal shared library written in C that is intended to take care of the OS-specific details when writing software that uses serial ports.

Prjpeppercorn includes programming tools for GateMate architecture from Cologne Chip. It also provides data needed to produce a nextpnr chip database Cologne Chip's GateMate architecture.

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

OpenBoardView is a viewer for BoardView files, which present the details of a printed circuit board (PCB). It comes with features such as:

• Dynamic part outline rendering, including complex connectors

• Annotations, for leaving notes about parts, nets, pins or location

• Configurable colour themes

• Configurable DPI to facilitate usage on 4K monitors

• Configurable for running on slower systems

• Reads FZ (with key), BRD, BRD2, BDV and BV* formats.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions and a System on Chip toolkit.

Camv-rnd is a viewer for PCB supporting gerber, excellon and g-code. It is part of the RiNgDove EDA suite.

Mcy is a tool to help digital designers and project managers understand and improve testbench coverage.

Xschem is an X11 schematic editor written in C and focused on hierarchical and parametric design. It can generate VHDL, Verilog or Spice netlists from the drawn schematic, allowing the simulation of the circuit.