SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

This package implements a functionality to create project files for supported tools and run them in batch or GUI mode. All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files,memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

Sigrok-cli is a command-line frontend for sigrok.

Cocotb-bus provides a set of utilities, test benches and reusable bus interfaces to be used with cocotb.

libpsf is a c++ library that reads Cadence PSF binary waveform files.

Open Logic implements commonly used design units in a reusable and vendor/tool-independent way. It is written following the VHDL 2008 standard, but can also be used from System Verilog.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

The codePyVcd Python library writes VCD files as specified in IEEE 1364-2005.

Nextpnr is a portable FPGA place and route tool.

Gerbv is a viewer for files in the Gerber format (RS-274X only), which is commonly used to represent printed circuit board (PCB) layouts. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place files.

The codePyUCIS library provides two APIs for creating and accessing coverage data via the UCIS data mode.

This package provides a library to turn Python into a hardware description and verification language.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI for sigrok.

The Dirtywave M8 Tracker is a portable sequencer and synthesizer, featuring 8 tracks of assignable instruments such as FM, waveform synthesis, virtual analog, sample playback, and MIDI output. It is powered by a Teensy micro-controller and inspired by the Gameboy tracker Little Sound DJ. m8c is a client for M8 Headless which allows one to install the M8 firmware on any Teensy.

Xoscope is a digital oscilloscope that can acquire signals from ALSA, ESD, and COMEDI sources. This package currently does not include support for ESD or COMEDI sources.

Xschem is an X11 schematic editor written in C and focused on hierarchical and parametric design. It can generate VHDL, Verilog or Spice netlists from the drawn schematic, allowing the simulation of the circuit.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

Libserialport is a minimal shared library written in C that is intended to take care of the OS-specific details when writing software that uses serial ports.

Magic is an interactive EDA layout tool. It can run DRC and LVS tests and can assist with automatic routing.

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.