_            _    _        _         _
      /\ \         /\ \ /\ \     /\_\      / /\
      \_\ \       /  \ \\ \ \   / / /     / /  \
      /\__ \     / /\ \ \\ \ \_/ / /     / / /\ \__
     / /_ \ \   / / /\ \ \\ \___/ /     / / /\ \___\
    / / /\ \ \ / / /  \ \_\\ \ \_/      \ \ \ \/___/
   / / /  \/_// / /   / / / \ \ \        \ \ \
  / / /      / / /   / / /   \ \ \   _    \ \ \
 / / /      / / /___/ / /     \ \ \ /_/\__/ / /
/_/ /      / / /____\/ /       \ \_\\ \/___/ /
\_\/       \/_________/         \/_/ \_____\/
yosys 0.66
Dependencies: abc-yosyshq@0.66 bash-minimal@5.2.37 editline@1.17.1 libffi@3.4.6 psmisc@23.7 pybind11@3.0.2 python@3.12.12 python-click@8.3.1 python-cxxheaderparser@1.7.0 readline@8.2.13 tcl@8.6.12 z3@4.13.0 zlib@1.3.1
Channel: guix
Location: gnu/packages/electronics.scm (gnu packages electronics)
Home page: https://yosyshq.net/yosys/
Licenses: ISC
Build system: gnu
Synopsis: Open synthesis suite for RTL code
Description:

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

Total packages: 1