_            _    _        _         _
      /\ \         /\ \ /\ \     /\_\      / /\
      \_\ \       /  \ \\ \ \   / / /     / /  \
      /\__ \     / /\ \ \\ \ \_/ / /     / / /\ \__
     / /_ \ \   / / /\ \ \\ \___/ /     / / /\ \___\
    / / /\ \ \ / / /  \ \_\\ \ \_/      \ \ \ \/___/
   / / /  \/_// / /   / / / \ \ \        \ \ \
  / / /      / / /   / / /   \ \ \   _    \ \ \
 / / /      / / /___/ / /     \ \ \ /_/\__/ / /
/_/ /      / / /____\/ /       \ \_\\ \/___/ /
\_\/       \/_________/         \/_/ \_____\/
yosys-clang-next 0.56-0.5aa7150
Dependencies: abc-yosyshq@0.58 bash-minimal@5.2.37 graphviz@7.0.1 gtkwave@3.4.0-0.bb978d9 libffi@3.4.6 psmisc@23.7 python@3.11.11 python-click@8.1.8 readline@8.2.13 tcl@8.6.12 xdot@1.4 z3@4.13.0 zlib@1.3.1 clang@13.0.1
Channel: electronics
Location: electronics/packages/synthesis.scm (electronics packages synthesis)
Home page: https://yosyshq.net/yosys/
Licenses: ISC
Synopsis: FPGA Verilog RTL synthesizer (Clang variant)
Description:

Yosys synthesizes Verilog-2005.

Total results: 1