Sc-surelog provides a Python interface to access Surelog.

Surelog is a Pre-processor, Parser, Elaborator and UHDM Compiler. It provides IEEE Design/TB C/C++ VPI and Python AST API.

GHDL analyses, elaborates and simulates VHDL sources. It may also be used as an experimental synthesizer backend.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

This package provides additional features and utilities for vhdl-mode, such as snippet selection via hydra, code navigation, code formatting, and code folding.

This package provides useful extensions on top of emacs vhdl-mode.

Emacs-fpga provides emacs facilities to interface with fpga & asic tools from major vendors.

VHDL-ts-mode provides syntax highlighting, indentation, imenu, which-func, navigation and basic beautify and completion features to navigate and edit VHDL files.

The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks.

The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Open Logic implements commonly used components in a reusable and vendor/tool-independent way.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

General cores is a library of widely used cores but still small enough not to require a dedicated repository.

fw-en-cl-fix provides low-level fixed-point functionality in both HDL and software languages. This includes basic arithmetic (addition, multiplication, etc) and number format conversions (with rounding and saturation).

A Tiny and Platform-Independent True Random Number Generator for any FPGA.

General cores is a library of widely used cores but still small enough not to require a dedicated repository.

This library provides some extra bits of code that are not found in the standard VHDL libraries.

Customizable microcontroller-like system on chip written in platform-independent VHDL.

Fpga-cores code is divided in synthesizable, simulation helpers and testbenches..

GHDL Language Server Protocol (LSP) is a server for VHDL based on GHDL.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

This package provides a program to transfer a bitstream to an FPGA. To use openfpgaloader without root privileges it is necessary to install the necessary udev rules. This can be done by extending udev-service-type in the operating-system configuration file with this package, as in:

(udev-rules-service 'openfpgaloader openfpgaloader #:groups '("plugdev")

Additionally, the plugdev group should be registered in the supplementary-groups field of your user-account declaration. Refer to info "(guix) Base Services" for examples.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

Yosys synthesizes Verilog-2005.