This package provides a minimal Linux loader as an UEFI program.

This package provides tools for signing EFI binaries.

This package provides an EFI toolchain for building programs that can run in the environment presented by Intel's EFI.

The EFI Analyzer checks EFI binaries and prints out header and section information.

PySpice implements a Ngspice binding and provides an oriented object API on top of SPICE, the simulation output is converted to Numpy arrays for convenience.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.

Fx2lafw is free firmware for Cypress FX2 chips which makes them usable as simple logic analyzer and/or oscilloscope hardware.

The codePyUCIS library provides two APIs for creating and accessing coverage data via the UCIS data mode.

Nextpnr is a portable FPGA place and route tool.

The Dirtywave M8 Tracker is a portable sequencer and synthesizer, featuring 8 tracks of assignable instruments such as FM, waveform synthesis, virtual analog, sample playback, and MIDI output. It is powered by a Teensy micro-controller and inspired by the Gameboy tracker Little Sound DJ. m8c is a client for M8 Headless which allows one to install the M8 firmware on any Teensy.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Pydigitalwavetools is a Python library to parse, write and format digital wave files in VCD format, a standardized ASCII format used to store simulation data from Verilog and other hardware description languages.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

This package is a waveform viewer for FST files.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

Project Trellis is a Nextpnr backend compatible with ECP5 FPGAs. The following features are currently available:

• logic slice functionality, including carries

• distributed RAM inside logic slices

• all internal interconnect

• basic IO, including tristate

• block RAM, using inference or manual instantiation

• multipliers using manual instantiation

• global networks and PLLs

• transcievers (DCUs.)

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

fftgen produces FFT hardware designs in Verilog.

Xoscope is a digital oscilloscope that can acquire signals from ALSA, ESD, and COMEDI sources. This package currently does not include support for ESD or COMEDI sources.

sby is a front-end program for Yosys-based formal hardware verification flows.

qucsrflayout command exports RF schematics to KiCad layouts and OpenEMS scripts.

Pcb-rnd is a Printed Circuit Board layout editor, part of the RiNgDove EDA suite.

Open source materials intended for reference by the IEEE standard 1076, as approved and published by the VHDL Analysis and Standardization Group.