Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

Magic is an interactive EDA layout tool. It can run DRC and LVS tests and can assist with automatic routing.

Mcy is a tool to help digital designers and project managers understand and improve testbench coverage.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

This is a pythonized, kind of reverse engineered version of original AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout are also taken from the original.

Sigrok-cli is a command-line frontend for sigrok.

Nextpnr is a portable FPGA place and route tool.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.

Camv-rnd is a viewer for PCB supporting gerber, excellon and g-code. It is part of the RiNgDove EDA suite.

Libsigrokdecode is a shared library written in C, which provides (streaming) protocol decoding functionality.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

Open Logic implements commonly used design units in a reusable and vendor/tool-independent way. It is written following the VHDL 2008 standard, but can also be used from System Verilog.

This package provides an extension to cocotb in the form of AXI, AXI lite, and AXI stream modules.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

Nextpnr is a portable FPGA place and route tool.

Prjpeppercorn includes programming tools for GateMate architecture from Cologne Chip. It also provides data needed to produce a nextpnr chip database Cologne Chip's GateMate architecture.

Nextpnr is a portable FPGA place and route tool.