This package provides a library to turn Python into a hardware description and verification language.

libsigrok is a shared library written in C which provides the basic hardware access drivers for logic analyzers and other supported devices, as well as input/output file format support.

Icarus Verilog is a Verilog/SystemVerilog EDA compiler that generates code employed by back-end tools. It operates compiling source code written in Verilog (IEEE-1364) and SystemVerilog (IEEE-1800) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

OpenROAD is an EDA toolkit for RTL to GDS design flows. It provides all necessary steps from VLSI designs to implement integrated chip physical designs, from RTL design to synthesized Verilog and routed layout. It includes tools for floorplanning, placement, clock tree synthesis, routing, parasitic extraction, and timing analysis.

Sch-rnd is a standalone and workflow agnostic schematics capture tool for PCB, part of the RiNgDove EDA suite.

Fx2lafw is free firmware for Cypress FX2 chips which makes them usable as simple logic analyzer and/or oscilloscope hardware.

This package provides a VHDL and SystemVerilog parser library for Python.

PyUVM is a Python implementation of the UVM, as defined in the IEEE 1800.2 standard. It uses cocotb to interact with simulators and schedule simulation events. It implements the most commonly used sections of the IEEE 1800.2 standard.

PyXHDL replaces HDL code by Python, generating VHDL (>= 2008) and Verilog (SystemVerilog >= 2012) code to be used for synthesis and simulation.

Fusesoc allows management and reuse of IP cores. It also aids for creating, building and simulating Soc solutions in EDA.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

This package contains the official KiCad project and worksheet templates.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

Library for describing geometrical objects and their physical and non-physical properties.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

The codePyVcd Python library writes VCD files as specified in IEEE 1364-2005.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.

GNUcap is a circuit analysis package used for EDA. It offers a general purpose circuit simulator and can perform DC and transient analyses, fourier analysis and AC analysis. The engine is designed to do true mixed-mode simulation.

netgen is a general purpose LVS management tool. It compares netlists of SPICE or verilog netlists circuits. This is commonly used as a part of toolchains in a process called LVS with the intent to verify that the layout of a circuit corresponds to the desired netlists.

This is a pythonized, kind of reverse engineered version of original AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout are also taken from the original.

The project Apycula provides tools to support development and generating bitstreams with Gowin FPGAs.

This package contains the official KiCad 3D model libraries.

ABIGAIL stands for the Application Binary Interface Generic Analysis and Instrumentation Library. It is a framework which aims at helping developers and software distributors to spot ABI-related issues like interface incompatibility in ELF shared libraries by performing a static analysis of the ELF binaries at hand.