The liberty-parser Python library provides a parser and data structures for the Liberty format, a standard file format used in EDA for example for timing information of digital circuits.

PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI for sigrok.

Lepton is an EDA tool set forked from gEDA/gaf in late 2016. EDA tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Lepton EDA includes tools for schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and PCB layout, and many other features.

UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.

Horizon is an EDA package supporting an integrated end-to-end workflow for PCB design, including from parts management and schematic entry to gerber export.

python-klayout is a standalone Python API of KLayout. This library supports OASIS and GDS2 file formats, editing of mask layouts, and verification such as DRC and LVS.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

Verilator is an EDA tool intended to transform the specified Verilog or SystemVerilog HDL code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single or multi-threaded .cpp and .h files.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

Libsigrokdecode is a shared library written in C, which provides (streaming) protocol decoding functionality.

This package provides a library of AST nodes for VHDL, SystemVerilog, and SystemC, with conversion between languages and to JSON.

GUI library for csxcad --- a library for describing geometrical objects and their properties. This library is used in appcsxcad which provides a standalone graphical frontend to {csxcad

Gerbv is a viewer for files in the Gerber format (RS-274X only), which is commonly used to represent printed circuit board (PCB) layouts. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place files.

Cocotb-bus provides a set of utilities, test benches and reusable bus interfaces to be used with cocotb.

Kicad is a program for the formation of printed circuit boards and electrical circuits. The software has a number of programs that perform specific functions, for example, pcbnew (Editing PCB), eeschema (editing electrical diagrams), gerbview (viewing Gerber files) and others. To use SQLite-backed database libraries, install the optional sqliteodbc package.

Sigrok-cli is a command-line frontend for sigrok.

The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions and a System on Chip toolkit.

code{Yosys-slang

This package contains the official KiCad schematic symbol libraries.

Charlib is an EDA tool used to extract timing and power characteristics from CMOS combinational and sequential standard-cells. It is compatible with ngspice and Xyce.

HAL is an EDA comprehensive netlist reverse engineering and manipulation framework. It provides a framework to parse netlists of arbitrary sources, e.g., FPGAs or ASICs, into a graph-based netlist representation, providing the necessary built-in tools for traversal and analysis of the included gates and nets.

Pcb-rnd is a Printed Circuit Board layout editor, part of the RiNgDove EDA suite.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.