Enter the query into the form above. You can look for specific version of a package by using @ symbol like this: gcc@10.
API method:
GET /api/packages?search=hello&page=1&limit=20
where search is your query, page is a page number and limit is a number of items on a single page. Pagination information (such as a number of pages and etc) is returned
in response headers.
If you'd like to join our channel webring send a patch to ~whereiseveryone/toys@lists.sr.ht adding your channel as an entry in channels.scm.
Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.
This package provides a program to transfer a bitstream to an FPGA. To use openfpgaloader without root privileges it is necessary to install the necessary udev rules. This can be done by extending udev-service-type in the operating-system configuration file with this package, as in:
(udev-rules-service 'openfpgaloader openfpgaloader #:groups '("plugdev")Additionally, the plugdev group should be registered in the supplementary-groups field of your user-account declaration. Refer to info "(guix) Base Services" for examples.
VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.
Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.
Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.
Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.
This plugin provides a shared library module for Yosys to implement logical synthesis of VHDL designs.
Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.
VUnit features the functionality needed to realize continuous and automated testing of HDL code.
VUnit features the functionality needed to realize continuous and automated testing of HDL code.
This package is a waveform viewer for FST files.
Bindings to SDL_image 2
A simple generic multithreaded tcp-server
Monocypher cryptographic library
Functional arrays and sets
Typed variants of various record-definition macros
libgit2 bindings
cond generics
Cache a procedure for a set time
easy drawing for programs on X displays
Tools for Scheme development
Command line option handling
The SLIB applicative routines for the arrays library
XML-RPC client/server