OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

Yosys synthesizes Verilog-2005.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

Libsigrokdecode is a shared library written in C, which provides (streaming) protocol decoding functionality.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

Fx2lafw is free firmware for Cypress FX2 chips which makes them usable as simple logic analyzer and/or oscilloscope hardware.

The Dirtywave M8 Tracker is a portable sequencer and synthesizer, featuring 8 tracks of assignable instruments such as FM, waveform synthesis, virtual analog, sample playback, and MIDI output. It is powered by a Teensy micro-controller and inspired by the Gameboy tracker Little Sound DJ. m8c is a client for M8 Headless which allows one to install the M8 firmware on any Teensy.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

fftgen produces FFT hardware designs in Verilog.

Open source materials intended for reference by the IEEE standard 1076, as approved and published by the VHDL Analysis and Standardization Group.

The JSON-for-VHDL library provides a parser to query JSON data structures from external files on disk. It provides a context to be used in the declarative section of design units.

ABC is a program for sequential logic synthesis and formal verification.

Camv-rnd is a viewer for PCB supporting gerber, excellon and g-code. It is part of the RiNgDove EDA suite.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

Nextpnr is a portable FPGA place and route tool.

Xschem is an X11 schematic editor written in C and focused on hierarchical and parametric design. It can generate VHDL, Verilog or Spice netlists from the drawn schematic, allowing the simulation of the circuit.

This package implements a functionality to create project files for supported tools and run them in batch or GUI mode. All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files,memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.

Sch-rnd is a standalone and workflow agnostic schematics capture tool for PCB, part of the RiNgDove EDA suite.

Xoscope is a digital oscilloscope that can acquire signals from ALSA, ESD, and COMEDI sources. This package currently does not include support for ESD or COMEDI sources.

Yosys synthesizes Verilog-2005.

Sigrok-cli is a command-line frontend for sigrok.