Enter the query into the form above. You can look for specific version of a package by using @ symbol like this: gcc@10.
API method:
GET /api/packages?search=hello&page=1&limit=20
where search is your query, page is a page number and limit is a number of items on a single page. Pagination information (such as a number of pages and etc) is returned
in response headers.
If you'd like to join our channel webring send a patch to ~whereiseveryone/toys@lists.sr.ht adding your channel as an entry in channels.scm.
Surelog is a Pre-processor, Parser, Elaborator and UHDM Compiler. It provides IEEE Design/TB C/C++ VPI and Python AST API.
Sc-surelog provides a Python interface to access Surelog.
GHDL analyses, elaborates and simulates VHDL sources. It may also be used as an experimental synthesizer backend.
Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.
VHDL-ts-mode provides syntax highlighting, indentation, imenu, which-func, navigation and basic beautify and completion features to navigate and edit VHDL files.
Emacs-fpga provides emacs facilities to interface with fpga & asic tools from major vendors.
This package provides useful extensions on top of emacs vhdl-mode.
This package provides additional features and utilities for vhdl-mode, such as snippet selection via hydra, code navigation, code formatting, and code folding.
Fpga-cores code is divided in synthesizable, simulation helpers and testbenches..
This library provides some extra bits of code that are not found in the standard VHDL libraries.
Customizable microcontroller-like system on chip written in platform-independent VHDL.
General cores is a library of widely used cores but still small enough not to require a dedicated repository.
General cores is a library of widely used cores but still small enough not to require a dedicated repository.
The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks.
The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.
A Tiny and Platform-Independent True Random Number Generator for any FPGA.
GHDL Language Server Protocol (LSP) is a server for VHDL based on GHDL.
Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.
This package provides a program to transfer a bitstream to an FPGA. To use openfpgaloader without root privileges it is necessary to install the necessary udev rules. This can be done by extending udev-service-type in the operating-system configuration file with this package, as in:
(udev-rules-service 'openfpgaloader openfpgaloader #:groups '("plugdev")Additionally, the plugdev group should be registered in the supplementary-groups field of your user-account declaration. Refer to info "(guix) Base Services" for examples.
VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.
This plugin provides a shared library module for Yosys to implement logical synthesis of VHDL designs.
Yosys synthesizes Verilog-2005.
Yosys synthesizes Verilog-2005.