This package provides tools for signing EFI binaries.

Libfst is a small library used to read and write FST format waveforms.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

Nextpnr is a portable FPGA place and route tool.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

The project Apycula provides tools to support development and generating bitstreams with Gowin FPGAs.

This package implements a functionality to create project files for supported tools and run them in batch or GUI mode. All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files,memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

This package provides an extension to cocotb in the form of AXI, AXI lite, and AXI stream modules.

This package is a waveform viewer for FST files.

Pydigitalwavetools is a Python library to parse, write and format digital wave files in VCD format, a standardized ASCII format used to store simulation data from Verilog and other hardware description languages.

Open Logic implements commonly used design units in a reusable and vendor/tool-independent way. It is written following the VHDL 2008 standard, but can also be used from System Verilog.

Sch-rnd is a standalone and workflow agnostic schematics capture tool for PCB, part of the RiNgDove EDA suite.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

sby-gui is a GUI for front-end driver program for codeyosys-based formal hardware verification flows.

The codePyVcd Python library writes VCD files as specified in IEEE 1364-2005.

This is a pythonized, kind of reverse engineered version of original AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout are also taken from the original.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

The codePyUCIS library provides two APIs for creating and accessing coverage data via the UCIS data mode.

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

Nextpnr is a portable FPGA place and route tool.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.