Libfst is a small library used to read and write FST format waveforms.

lctime extracts timing and power characteristics of CMOS standard-cells. It simulates the netlists of the cells with ngspice and writes the characterization result in a liberty library file.

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

Surelog is a pre-processor, parser, elaborator and UHDM compiler. It provides IEEE design, a C/C++ VPI and a Python AST API.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

sby-gui is a GUI for front-end driver program for codeyosys-based formal hardware verification flows.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Slang is a software library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code. It comes with an executable tool that can compile and lint any SystemVerilog project, but it is also intended to be usable as a front end for synthesis tools, simulators, linters, code editors, and refactoring tools.

Sch-rnd is a standalone and workflow agnostic schematics capture tool for PCB, part of the RiNgDove EDA suite.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

This package provides a VHDL and SystemVerilog parser library for Python.

Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

fftgen produces FFT hardware designs in Verilog.

This package provides an extension to cocotb in the form of AXI, AXI lite, and AXI stream modules.

This package provides a library of AST nodes for VHDL, SystemVerilog, and SystemC, with conversion between languages and to JSON.

qucsrflayout command exports RF schematics to KiCad layouts and OpenEMS scripts.

Prjpeppercorn includes programming tools for GateMate architecture from Cologne Chip. It also provides data needed to produce a nextpnr chip database Cologne Chip's GateMate architecture.

nextpnr is an EDA, portable and vendor neutral FPGA place and route tool.

OpenROAD is an EDA toolkit for RTL to GDS design flows. It provides all necessary steps from VLSI designs to implement integrated chip physical designs, from RTL design to synthesized Verilog and routed layout. It includes tools for floorplanning, placement, clock tree synthesis, routing, parasitic extraction, and timing analysis.

LibreLane is an EDA ASIC infrastructure library based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design exploration and optimization.

gdstk is a library for creation and manipulation of GDSII layout files which are commonly used for EDA and chip design.

Verilator is an EDA tool intended to transform the specified Verilog or SystemVerilog HDL code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single or multi-threaded .cpp and .h files.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.