Project Trellis is a Nextpnr backend compatible with ECP5 FPGAs. The following features are currently available:

• logic slice functionality, including carries

• distributed RAM inside logic slices

• all internal interconnect

• basic IO, including tristate

• block RAM, using inference or manual instantiation

• multipliers using manual instantiation

• global networks and PLLs

• transcievers (DCUs.)

lln-libparse is a SWIG-based Python wrapper around Yosys' libparse, enabling dotlib file parsing.

PySpice implements a Ngspice binding and provides an oriented object API on top of SPICE, the simulation output is converted to Numpy arrays for convenience.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

Pcb-rnd is a Printed Circuit Board layout editor, part of the RiNgDove EDA suite.

This package contains the official KiCad 3D model libraries.

netgen is a general purpose LVS management tool. It compares netlists of SPICE or verilog netlists circuits. This is commonly used as a part of toolchains in a process called LVS with the intent to verify that the layout of a circuit corresponds to the desired netlists.

Sch-rnd is a standalone and workflow agnostic schematics capture tool for PCB, part of the RiNgDove EDA suite.

PyRTL provides a collection of classes for Pythonic RTL-level design, simulation, tracing, and testing, suitable for teaching and research.

sby is an EDA front-end program for Yosys-based formal hardware verification flows.

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

KLayout is EDA software. It is a scriptable VLSI layout editor used for visualizing and editing mask data, transcoding between different file formats (GDSII and OASIS), executing DRC, LVS verification, and drawing of chip cross-sections basked on mask data.

Slang is a software library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code. It comes with an executable tool that can compile and lint any SystemVerilog project, but it is also intended to be usable as a front end for synthesis tools, simulators, linters, code editors, and refactoring tools.

This package provides a VHDL compiler and simulator.

Fx2lafw is free firmware for Cypress FX2 chips which makes them usable as simple logic analyzer and/or oscilloscope hardware.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

LibreLane is an EDA ASIC infrastructure library based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design exploration and optimization.

qrouter is an ASICs tool intended for digital chip design. It creates the detailed routes for layouts of digital circuits and generates metal layers and vias.

ciel downloads and installs open-source PDKs which are used for chip design and EDA.

VUnit features the functionality needed to realize continuous and automated testing of HDL code.

This package contains the official KiCad schematic symbol libraries.

Libsigrokdecode is a shared library written in C, which provides (streaming) protocol decoding functionality.

The liberty-parser Python library provides a parser and data structures for the Liberty format, a standard file format used in EDA for example for timing information of digital circuits.

libdwarf is a library that handles the DWARF debugging information format.