Libfst is a small library used to read and write FST format waveforms.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

This package provides a library to turn Python into a hardware description and verification language.

PySpice implements a Ngspice binding and provides an oriented object API on top of SPICE, the simulation output is converted to Numpy arrays for convenience.

libsigrok is a shared library written in C which provides the basic hardware access drivers for logic analyzers and other supported devices, as well as input/output file format support.

Sigrok-cli is a command-line frontend for sigrok.

qucsrflayout command exports RF schematics to KiCad layouts and OpenEMS scripts.

libpsf is a c++ library that reads Cadence PSF binary waveform files.

SystemC is a C++ library for modeling concurrent systems, and the reference implementation of IEEE 1666-2011. It provides a notion of timing as well as an event-driven simulations environment. Due to its concurrent and sequential nature, SystemC allows the description and integration of complex hardware and software components. To some extent, SystemC can be seen as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC provides sophisticated mechanisms that offer high abstraction levels on components interfaces. This, in turn, facilitates the integration of systems using different abstraction levels.

Qucsator-rf is a command line driven circuit simulator targeted for RF and microwave circuits. It takes a network list in a certain format as input and outputs an XML dataset.

Open Logic implements commonly used design units in a reusable and vendor/tool-independent way. It is written following the VHDL 2008 standard, but can also be used from System Verilog.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

Project Trellis is a Nextpnr backend compatible with ECP5 FPGAs. The following features are currently available:

• logic slice functionality, including carries

• distributed RAM inside logic slices

• all internal interconnect

• basic IO, including tristate

• block RAM, using inference or manual instantiation

• multipliers using manual instantiation

• global networks and PLLs

• transcievers (DCUs.)

Nextpnr is a portable FPGA place and route tool.

ABC is a program for sequential logic synthesis and formal verification.

sby-gui is a GUI for front-end driver program for codeyosys-based formal hardware verification flows.

fftgen produces FFT hardware designs in Verilog.

The Dirtywave M8 Tracker is a portable sequencer and synthesizer, featuring 8 tracks of assignable instruments such as FM, waveform synthesis, virtual analog, sample playback, and MIDI output. It is powered by a Teensy micro-controller and inspired by the Gameboy tracker Little Sound DJ. m8c is a client for M8 Headless which allows one to install the M8 firmware on any Teensy.

This package provides a VHDL compiler and simulator.

UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

Ngspice is a mixed-level/mixed-signal circuit simulator. It includes Spice3f5, a circuit simulator, and Xspice, an extension that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions and a System on Chip toolkit.