Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. The package contains libraries for schematic capture, visualization and components. The following simulation kernels are supported:

• Ngspice (recommended)

• Xyce

• SpiceOpus

• Qucsator (non-SPICE)

Sigrok-cli is a command-line frontend for sigrok.

nextpnr is an EDA, portable and vendor neutral FPGA place and route tool.

PyXHDL replaces HDL code by Python, generating VHDL (>= 2008) and Verilog (SystemVerilog >= 2012) code to be used for synthesis and simulation.

This package provides a library of AST nodes for VHDL, SystemVerilog, and SystemC, with conversion between languages and to JSON.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

Fx2lafw is free firmware for Cypress FX2 chips which makes them usable as simple logic analyzer and/or oscilloscope hardware.

lln-libparse is a SWIG-based Python wrapper around Yosys' libparse, enabling dotlib file parsing.

Gerbv is a viewer for files in the Gerber format (RS-274X only), which is commonly used to represent printed circuit board (PCB) layouts. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place files.

sby-gui is a GUI for front-end driver program for codeyosys-based formal hardware verification flows.

This repository contains the official KiCad documentation.

Xoscope is a digital oscilloscope that can acquire signals from ALSA, ESD, and COMEDI sources. This package currently does not include support for ESD or COMEDI sources.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

This package provides a library to turn Python into a hardware description and verification language.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.

Icarus Verilog is a Verilog/SystemVerilog EDA compiler that generates code employed by back-end tools. It operates compiling source code written in Verilog (IEEE-1364) and SystemVerilog (IEEE-1800) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

gdstk is a library for creation and manipulation of GDSII layout files which are commonly used for EDA and chip design.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI for sigrok.

Eqy is an EDA front-end driver program for Yosys-based formal hardware equivalence checking. It performs formal verification on two designs, such as ensuring that a synthesis tool has not introduced functional changes into a design, or ensuring that a design refactor preserves correctness in all conditions.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.