OpenBoard is a teaching software for interactive whiteboard designed primarily for use in schools and universities. It can be used both with interactive whiteboards or in a dual-screen setup with a pen-tablet display and a beamer.

Anki is a program which makes remembering things easy. Because it's a lot more efficient than traditional study methods, you can either greatly decrease your time spent studying, or greatly increase the amount you learn.

Anyone who needs to remember things in their daily life can benefit from Anki. Since it is content-agnostic and supports images, audio, videos and scientific markup (via LaTeX), the possibilities are endless. For example:

• Learning a language

• Studying for medical and law exams

• Memorizing people's names and faces

• Brushing up on geography

• Mastering long poems

• Even practicing guitar chords!

FET is a program for automatically scheduling the timetable of a school, high-school or university. It uses a fast and efficient timetabling algorithm.

Usually, FET is able to solve a complicated timetable in maximum 5-20 minutes. For extremely difficult timetables, it may take a longer time, a matter of hours.

Tux, of Math Command is an educational math tutorial game starring Tux, the Linux penguin, in which you play the part of Commander Tux, as he defends his friends from an attack of math equations. Comets are crashing towards the friendly penguins in their igloos, and you must destroy the comets by solving their equations.

TuxMath also includes Factoroids, a game that gives practice in factoring numbers and simplifying fractions, as well as zapping rocks floating through space.

GNU MDK is the Mix Development Kit, an emulation of the pedagogical computer MIX and its assembly language MIXAL. MIX has a virtual CPU with standard features such as registers, memory cells, an overflow toggle, comparison flags, input-output devices, and a set of binary instructions. The package includes a compiler, a virtual machine, a GUI for the virtual machine, and more.

This package provides EFI tools for EFI key management and EFI variable management.

This package provides an EFI toolchain for building programs that can run in the environment presented by Intel's EFI.

The EFI Analyzer checks EFI binaries and prints out header and section information.

This package provides tools for signing EFI binaries.

This package provides a minimal Linux loader as an UEFI program.

OSVVM is a verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability for FPGA or ASIC verification.

ABC is a program for sequential logic synthesis and formal verification. This is the Yosyshq fork of ABC.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

This package is a waveform viewer for FST files.

Sigrok-cli is a command-line frontend for sigrok.

This is a pythonized, kind of reverse engineered version of original AACircuit written by Andreas Weber in Borland Delphi. The idea and GUI layout are also taken from the original.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

This package provides the look and feel of Python unit testing to cocotb, removing the need of manipulating Makefiles.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

This package implements a functionality to create project files for supported tools and run them in batch or GUI mode. All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files,memory initialization files, IP description files etc). Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set.

PySpice implements a Ngspice binding and provides an oriented object API on top of SPICE, the simulation output is converted to Numpy arrays for convenience.

Coroutine based cosimulation test bench environment for verifying VHDL and Verilog RTL using Python.