Pcb-rnd is a Printed Circuit Board layout editor, part of the RiNgDove EDA suite.

Eqy is a front-end driver program for Yosys-based formal hardware equivalence checking. It performs formal verification on two designs, such as ensuring that a synthesis tool has not introduced functional changes into a design, or ensuring that a design refactor preserves correctness in all conditions.

ABC is a program for sequential logic synthesis and formal verification.

Sigrok-cli is a command-line frontend for sigrok.

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

PySpice implements a Ngspice binding and provides an oriented object API on top of SPICE, the simulation output is converted to Numpy arrays for convenience.

sby is a front-end program for Yosys-based formal hardware verification flows.

Xyce is a SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution.

sby is a front-end program for Yosys-based formal hardware verification flows.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

OpenBoardView is a viewer for BoardView files, which present the details of a printed circuit board (PCB). It comes with features such as:

• Dynamic part outline rendering, including complex connectors

• Annotations, for leaving notes about parts, nets, pins or location

• Configurable colour themes

• Configurable DPI to facilitate usage on 4K monitors

• Configurable for running on slower systems

• Reads FZ (with key), BRD, BRD2, BDV and BV* formats.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp. For synthesis, the compiler generates netlists in the desired format.

qucsrflayout command exports RF schematics to KiCad layouts and OpenEMS scripts.

This package provides a library to turn Python into a hardware description and verification language.

PulseView is a Qt based logic analyzer, oscilloscope and MSO GUI for sigrok.

Cocotb-bus provides a set of utilities, test benches and reusable bus interfaces to be used with cocotb.

Gerbv is a viewer for files in the Gerber format (RS-274X only), which is commonly used to represent printed circuit board (PCB) layouts. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place files.

Nextpnr is a portable FPGA place and route tool.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

VSG lets you define a VHDL coding style and provides a command-line tool to enforce it.

Open source materials intended for reference by the IEEE standard 1076, as approved and published by the VHDL Analysis and Standardization Group.

libpsf is a c++ library that reads Cadence PSF binary waveform files.

Magic is an interactive EDA layout tool. It can run DRC and LVS tests and can assist with automatic routing.