Migen FHDL is a Python library that replaces the event-driven paradigm of Verilog and VHDL with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and allows the design's logic to be constructed by a Python program.

Sigrok-cli is a command-line frontend for sigrok.

Yosys consist on a framework of RTL synthesis tools. It currently has extensive Verilog-2005 support, and performs synthesis of VHDL code using external plugins. It provides a basic set of synthesis algorithms for various application domains, including FPGAs and ASICs.

This package is a waveform viewer for FST files.

Hdlmake helps manage and share HDL code by automatically finding file dependencies, writing synthesis and simulation Makefiles.

Fusesoc allows management and reuse of IP cores. It also aids for creating, building and simulating Soc solutions in EDA.

Route-rnd is a generic external autorouter for PCB using tEDAx file format, part of the RiNgDove EDA suite.

GUI library for csxcad --- a library for describing geometrical objects and their properties. This library is used in appcsxcad which provides a standalone graphical frontend to {csxcad

OSVVM is a verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability for FPGA or ASIC verification.

Libserialport is a minimal shared library written in C that is intended to take care of the OS-specific details when writing software that uses serial ports.

PyXHDL replaces HDL code by Python, generating VHDL (>= 2008) and Verilog (SystemVerilog >= 2012) code to be used for synthesis and simulation.

The project Apycula provides tools to support development and generating bitstreams with Gowin FPGAs.

Surf is a python library with support functions for VHDL gateware digital design. It provides implementation modules compatible with FPGA and ASIC design.

PySpice implements a Ngspice binding and provides an oriented object API on top of SPICE, the simulation output is converted to Numpy arrays for convenience.

Pydigitalwavetools is a Python library to parse, write and format digital wave files in VCD format, a standardized ASCII format used to store simulation data from Verilog and other hardware description languages.

libpsf is a c++ library that reads Cadence PSF binary waveform files.

libsigrok is a shared library written in C which provides the basic hardware access drivers for logic analyzers and other supported devices, as well as input/output file format support.

This package contains the official KiCad schematic symbol libraries.

The codePyUCIS library provides two APIs for creating and accessing coverage data via the UCIS data mode.

python-klayout is a standalone Python API of KLayout. This library supports OASIS and GDS2 file formats, editing of mask layouts, and verification such as DRC and LVS.

Project Trellis is a Nextpnr backend compatible with ECP5 FPGAs. The following features are currently available:

• logic slice functionality, including carries

• distributed RAM inside logic slices

• all internal interconnect

• basic IO, including tristate

• block RAM, using inference or manual instantiation

• multipliers using manual instantiation

• global networks and PLLs

• transcievers (DCUs.)

HAL is an EDA comprehensive netlist reverse engineering and manipulation framework. It provides a framework to parse netlists of arbitrary sources, e.g., FPGAs or ASICs, into a graph-based netlist representation, providing the necessary built-in tools for traversal and analysis of the included gates and nets.

PyUVM is a Python implementation of the UVM, as defined in the IEEE 1800.2 standard. It uses cocotb to interact with simulators and schedule simulation events. It implements the most commonly used sections of the IEEE 1800.2 standard.

sby is an EDA front-end program for Yosys-based formal hardware verification flows.